VHDL Code for Full Adder

The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are High. Cout is High, when two or more inputs are High. VHDL Code for full adder can also be constructed with 2 half adder Port mapping in to full adder.

Full Adder Truth Table

Full Adder Logic Circuit

VHDL Code for Full Adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_adder_vhdl_code is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end full_adder_vhdl_code; architecture gate_level of full_adder_vhdl_code is begin S 
Testbench VHDL Code for Full Adder
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Testbench_full_adder IS END Testbench_full_adder; ARCHITECTURE behavior OF Testbench_full_adder IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT full_adder_vhdl_code PORT( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; S : OUT std_logic; Cout : OUT std_logic ); END COMPONENT; --Inputs signal A : std_logic := '0'; signal B : std_logic := '0'; signal Cin : std_logic := '0'; --Outputs signal S : std_logic; signal Cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: full_adder_vhdl_code PORT MAP ( A => A, B => B, Cin => Cin, S => S, Cout => Cout ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; -- insert stimulus here A 
Output Waveform for full adder VHDL Code

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Categories VHDL Tags full adder vhdl code
13 thoughts on “VHDL Code for Full Adder”
sarah.karimi8
I have typed all the same as the code above both for model and testbench. But in simulation I don’t see the square wave. I just see flat lines. Could you comment what I must change? Reply
Theodoros Davidopoulos
What do i do about that? I have the same code, small differences, but i get this message. My syntax is correct. Error (10533): VHDL Wait Statement error at FULL_ADDER_TB.vhd(32): Wait Statement must contain condition clause with UNTIL keyword Reply
Deshant Devkota
Can someone tell me how to run it in model sim. Reply
BALASUBRAMANIYAM.S
I have a problem when compile the program. 
The error is EOF syntax error. 
I want the reason , y it’s happend. Reply